Cold Electronics Review

Session

Plenary

12 Oct 2016, 13:30

BNL Instrumentation

Contribution list Timetable

41. Front-End and ADC ASIC Design

Dr Shaorui Li (BNL)

12/10/2016, 13:30

43. FE and ADC ASIC Testing Summary

Dr Shanshan Gao (Brookhaven National Laboratory)

12/10/2016, 14:30

44. Lessons Learned from MicroBooNE/35-ton

Dr Veljko Radeka (BNL)

12/10/2016, 15:20

45. Plans for ProtoDUNE/SBND Integrated System Testing

Matthew Worcester (BNL), Theresa Shaw (FNAL)

12/10/2016, 16:00

61. Joint Discussion

12/10/2016, 16:30

53. Cold Electronics Risks & Plans for Risk Mitigation

Matthew Worcester (BNL)

13/10/2016, 14:00

54. Potential Catastrophic Failure Modes & System Protections

Dr Veljko Radeka (BNL)

13/10/2016, 14:30

55. Cold Electronics QA/QC Plan

Dean Shooltz (MSU)

13/10/2016, 15:15

56. SBND/ProtoDUNE Schedule

Matthew Worcester (BNL)

13/10/2016, 15:45

57. Tour of Electronics Lab - Group 2

Dr Hucheng Chen (Brookhaven National Lab), Dr Shanshan Gao (Brookhaven National Laboratory)

13/10/2016, 16:15