Upstream DAQ Tech meeting

Thursday 8 Jul 2021, 07:00 → 08:21 US/Central

 

https://cern.zoom.us/j/68022868314

 

1 Current sprint

dunedaq-2.8.0 / FW-2.0.0

Main objectives
- TPG chain
- Ethernet readout (only software for now)

Speakers: Ivana Hristova (STFC RAL), Jim Brooke, Dr Konstantinos Manolopoulos (Rutherford Appleton Laboratory), Konstantinos Manolopoulos (Rutherford Appleton Laboratory), Roland Sipos (CERN), Stoyan Trilov

2 Readout (FW & SW)

Technical developments & future plans on Readout Subsystem.

Speakers: Antony Earle (University of Sussex), Filiberto Bonini (Brookhaven National Laboratory), Mr Florian Grotschla (CERN), Ivana Hristova (STFC RAL), Konstantinos Manolopoulos (Rutherford Appleton Laboratory), Konstantinos Manolopoulos (Rutherford Appleton Laboratory), Roland Sipos (CERN), Shyam Bhuller (University of Bristol)

Frimware (K. Manolopoulos)

• work on-going with fw release v1.2
  • sorting out details on connecting Data Reception to the top level and wibulators
  • several conflicts had to be sorted out
  • once done will proceed with a ZCU hw test
  • rest of gitlab repos (dtp-sim, dtp-controls) already tagged

 

 

Software

• Bug fixes, improvements, and QoL changes from Florian: https://github.com/DUNE-DAQ/readout/commits/develop
• Error registry -> time window gaps in LB handled gracefully.
• Full attention on TP chain now. FakeTPSource, TP buffering, interfacing with DS

Felix-pie (A.Thea A.Earle)

• Tested ipbus integration on FLX712 card with ipbus example register and shown working.
• Current task is integration of dummy processing block to demonstrate splitting and capture of ADC links, test data output on "6th" link and successful control using ipbus.
• Task after this is integration of a real processing block which should be simplified having integrated the dummy block

3 Trigger Primitives (FW & SW)

Technical developments & future plans on TP specific firmware and software.

Speakers: Antony Earle (University of Sussex), Ivana Hristova (STFC RAL), Konstantinos Manolopoulos (Rutherford Appleton Laboratory), Kunal Kothekar

Software: 

- Software TPG port: https://github.com/DUNE-DAQ/readout/tree/swtpg-port
Needs follow up on enabling induction plane and parallel access to frames.

4 Timing

Technical developments & future plans

Speakers: David Cussans (University of Bristol), Stoyan Trilov

F/ware , S/ware

• Concentrating on 2.8 release
  • Aimed at providing support for initial PD-2 activities
  • Does include support for AFC+FIB (FPGA carrier + Fibre Interface Boards)
• Some discussion with timing integration with ND readout teams.

H/Ware

• MicroTCA crate has arrived at CERN
  • Power modules, crate controller (MCH), programming controller (JSM) will be shipped when additional carrier cards (AFC) arrive in Bristol and are tested with FIB
• (MIB) MicroTCA Interface Board comissioning stalled waiting for effort.

Integration

• Need to verify White-Rabit <--> DUNE timing system clock stability ( Current plan, following discussion with VD electronics coordinator ). Initial tests planned for this month.
• Will be supporting initial cold box tests with existing hardware.

Staffing

• Adam Barcock, on RAL graduate training scheme has started work (funded by drawing on working allowance). After delay has been registered as a DUNE collaborator and able to contribute to code.
  • Starting out by porting timing firmware to Digilent Nexsys Video board since the Enclustra PM3/AX3 combination not available until November and we need a platform to allow readout groups to develop interface with timing system

 

5 Integration

Integration status at:
- CERN
- Bristol
- UPenn
- ICEBERG

Speakers: Kunal Kothekar, Roland Sipos (CERN), Shyam Bhuller (University of Bristol)

Bristol Test Stand:

What has been done:

- tried dune-daq readout 2.6.0 at the test stand, was able to receive data from both data sources and for both felix ups product versions using the PEXInit 24ch ATLAS-tDAQ firmware. Was unable to recieve any data from the 12ch vanilla bitfile produced using felixpy. 

-  The captures were taken from the internal emulator and zcu102 with 2.6 in a similar fashion as those taken previously with fdaq.

- emulator configuration patterns are uploaded the dtp-patterns : https://gitlab.cern.ch/dune-daq/readout/dtp-patterns/-/tree/master/EMUInput (with REAME on how to use them)

- Also the script to generate the emuconfig pattern is uploaded to dtp-simulation.

 What needs to be done:

 - test felix v1_1_3 with register changes (fdaq)

 - test felix software suite distribution (separate build to ups product) and compare results

 - try newer felixpy build with readout

- Analyze the captures taken with 2.6

- test the firmware 1.2 release with zcu102.

 

6 AOB