Ethernet based Readout for FD-VD
Monday, 2 August 2021 -
08:00
Monday, 2 August 2021
08:00
Introduction
-
Giovanna Lehmann
(CERN)
Introduction
Giovanna Lehmann
(CERN)
08:00 - 08:05
08:05
The Vertical Drift Far Detector
-
Francesco Pietropaolo
(CERN)
Francesco Pietropaolo
(CERN)
The Vertical Drift Far Detector
Francesco Pietropaolo
(CERN)
Francesco Pietropaolo
(CERN)
08:05 - 08:20
08:25
Overview of the top electronics readout system
-
Dario Autiero
(IPNL)
Overview of the top electronics readout system
Dario Autiero
(IPNL)
08:25 - 08:40
08:45
The DUNEDAQ readout system
-
Roland Sipos
(CERN)
The DUNEDAQ readout system
Roland Sipos
(CERN)
08:45 - 08:55
08:55
Using smart NICs for initial SW driven readout of the VD top electronics
-
Roland Sipos
(CERN)
Using smart NICs for initial SW driven readout of the VD top electronics
Roland Sipos
(CERN)
08:55 - 09:10
09:15
Experience at RAL TD with FW/HW ethernet COTS boards
-
Rob Halsall
Experience at RAL TD with FW/HW ethernet COTS boards
Rob Halsall
09:15 - 09:30
09:35
Estimated FELIX FW resources required for VD (with FW extensions to Ethernet)
-
Konstantinos Manolopoulos
(Rutherford Appleton Laboratory)
Estimated FELIX FW resources required for VD (with FW extensions to Ethernet)
Konstantinos Manolopoulos
(Rutherford Appleton Laboratory)
09:35 - 09:50
09:55
FW platforms for the future
-
Roy Wastie
(University of Oxford)
Giles Barr
(Oxford University)
FW platforms for the future
Roy Wastie
(University of Oxford)
Giles Barr
(Oxford University)
09:55 - 10:10
10:15
Discussion, planning and timelines
-
Giovanna Lehmann
(CERN)
Roland Sipos
(CERN)
Alessandro Thea
(STFC Rutherford Appleton Laboratory)
Discussion, planning and timelines
Giovanna Lehmann
(CERN)
Roland Sipos
(CERN)
Alessandro Thea
(STFC Rutherford Appleton Laboratory)
10:15 - 11:00