Upstream DAQ Tech meeting

Thursday 5 Aug 2021, 07:00 → 08:21 US/Central

 

https://cern.zoom.us/j/68022868314

 

07:00 → 07:15 Current sprint

dunedaq-2.8.0 / FW-2.0.0

Main objectives
- TPG chain
- Ethernet readout (only software for now)

Speakers: Ivana Hristova (STFC RAL), Jim Brooke, Dr Konstantinos Manolopoulos (Rutherford Appleton Laboratory), Konstantinos Manolopoulos (Rutherford Appleton Laboratory), Roland Sipos (CERN), Stoyan Trilov

- Shyam prepared commit hashes for the new felix UPS product and figured out some issues with the emu_confgen. This application was also added to flxlibs.

- Florian follows minidaqapp integration with df and ds

- Readout + flxlibs tagged today late afternoon (CERN time)

07:15 → 07:30 Readout (FW & SW)

Technical developments & future plans on Readout Subsystem.

Speakers: Antony Earle (University of Sussex), Filiberto Bonini (Brookhaven National Laboratory), Mr Florian Grotschla (CERN), Ivana Hristova (STFC RAL), Konstantinos Manolopoulos (Rutherford Appleton Laboratory), Konstantinos Manolopoulos (Rutherford Appleton Laboratory), Roland Sipos (CERN), Shyam Bhuller (University of Bristol)

Firmware

• During testing for the intermediate fw release found a couple of bugs in the Wibulator and the hfbutler script. Erdem, Tony and Kunal are investigating
• D.C is working on WIB2 Unpacker and its integration with the Data Router
• Finished fw changes for the new TP format (Kostas)
  • Ivana to implement a new set of test files

Felix-Pie

• Was encountering timing issues building design with test processing block
• Built initial design and was able to use ipbus to communicate with test 32b sink blocks
• When running fdaq, random block errors where seen. Checked design and noticed some errors in signal definitions
• Fixed and currently running build for testing this afternoon

 

Felix Software

• Created new proposed software suite distribution which works with felix-pie builds. Contains regmap version with dune-ipbus version and includes new package flxcard_py.
• Created flxlibs_emu_confgen app to create simple internal emulator configurations in flxlibs
• Updated software suite hack and the internal emulator wiki in flxlibs

07:30 → 07:45 Trigger Primitives (FW & SW)

Technical developments & future plans on TP specific firmware and software.

Speakers: Antony Earle (University of Sussex), Ivana Hristova (STFC RAL), Konstantinos Manolopoulos (Rutherford Appleton Laboratory), Kunal Kothekar

TP simulation and software (I. Hristova)

1. Simulation

- preparing and debugging WIB2 patterns (data reception, unpacker)

 

2. Readout software

- using development branches for 2.8, works fine

- test app which implements reading fake TPs from file and preforms the following processing

- raw hits are stitched based on the wire number and stored as TriggerPrimitive

- TriggerPrimitive's are stored in TPSet's within a given time window based on the hit start time

- need few more hours/days for more debugging

- next stage will be the integration in the readout package

 

07:45 → 08:00 Timing

Technical developments & future plans

Speakers: David Cussans (University of Bristol), Stoyan Trilov

Hardware

• Of the ten new FMC boards one has been sent to RAL and one to CERN for tests. One will be sent to Nuno Barass for calibration system integration
• Delivery of AFC carriers (to mount FIBs on) delayed but should arrive in Bristol soon.

Firmware

• Version 6.0.0 tagged as a pre-release. Being validated before being released for use with "2.8 sprint".
  • Includes the ability to read MAC address from PROM and use RARP for IP address allocation.
• Port of timing firmware to Digilent Nexsys Video board almost complete (so that we aren't limited by the lack of availability of Enclustra AX3+PM3)
• Next task - support for MIB

Software

• Work for 2.8 sprint.
  • Integration with Run Control
  • Integration with operational monitoring

Integration

• Tests starting to evaluate linking White Rabbit with the DUNE Timing system (DTS)
  • Initial results encouraging.
    • Clock stability good (although only "one hop" tested so far)
  • Working to be able to time-stamp same signal on WR and DTS

 

•  

 

08:00 → 08:15 Integration

Integration status at:
- CERN
- Bristol
- UPenn
- ICEBERG

Speakers: Kunal Kothekar, Roland Sipos (CERN), Shyam Bhuller (University of Bristol)

Bristol Test stand:

What needs to be done:

• try additional QSFP on ZCU to play data along 8 fibers.
• check v1.2.0 test UPS product is functional/ compare to local version built

08:15 → 08:20 AOB