Upstream DAQ Tech meeting

US/Central
    • 07:00 07:15
      Current sprint 15m

      dunedaq-2.8.0 / FW-2.0.0

      Main objectives
      - TPG chain
      - Ethernet readout (only software for now)

      Speakers: Ivana Hristova (STFC RAL), Jim Brooke, Konstantinos Manolopoulos (Rutherford Appleton Laboratory), Dr Konstantinos Manolopoulos (Rutherford Appleton Laboratory), Roland Sipos (CERN), Stoyan Trilov
    • 07:15 07:30
      Readout (FW & SW) 15m

      Technical developments & future plans on Readout Subsystem.

      Speakers: Antony Earle (University of Sussex), Filiberto Bonini (Brookhaven National Laboratory), Mr Florian Grotschla (CERN), Ivana Hristova (STFC RAL), Konstantinos Manolopoulos (Rutherford Appleton Laboratory), Konstantinos Manolopoulos (Rutherford Appleton Laboratory), Roland Sipos (CERN), Shyam Bhuller (University of Bristol)

      Firmware

      • Firmware release v1.2.0 circulated on Slack
      • Asked for various people to follow testing instructions, run sim and hw tests and give us any feedback
      • Kunal is already updating the Testing Readme 
      • Plan is to release end of this week

      felix-pie

      • Found ipbus issue causing header packet errors. Two clocks, (25MHz/40MHz) used in ipbus comms when there should only be one
      • Updated design has seemingly fixed the error
      • Updated dummy design with ipbus clock fix and single axis 32b sink and wibulator going back to central router built
      • Sink can capture data successfully from link
      • fdaq shows data from wibulator appearing at central router and being readout, but data dump only has first line of test pattern
      • Building debug project to investigate
    • 07:30 07:45
      Trigger Primitives (FW & SW) 15m

      Technical developments & future plans on TP specific firmware and software.

      Speakers: Antony Earle (University of Sussex), Ivana Hristova (STFC RAL), Konstantinos Manolopoulos (Rutherford Appleton Laboratory), Kunal Kothekar

      TP software (I. Hristova)

      - Setup dunedaq-2.8 environment

      - daq_application configured to run 1 TP link

      - FakeCardReader reading TPs from fake PD1 input binary file

      - Ongoing - integrating the conversion of old PD1 hit format to new TP format (overlay)

       

      TP simulation (I. Hristova)

      - Updating dtp-simulation and dtp-patterns REAME files

      - dpt-controls needs update too

      - Current work in branch https://gitlab.cern.ch/dune-daq/readout/dtp-simulation/-/tree/hristova/rawhit_tp_format

    • 07:45 08:00
      Timing 15m

      Technical developments & future plans

      Speakers: David Cussans (University of Bristol), Stoyan Trilov
      • Released firmware tag v6.0.0 . Completes firmware work in conjunction with 2.8 sprint
      • Have met milestone of being ready for cold-box tests by using existing, rather than new h/ware.
      • Timing system example firmware ported to new FPGA carrier ( Digilent Nexsys Video ) since "work horse" Enclustra AX3/PM3 out of stock until end of year
        • Will be used by
          • UK timing team
          • FD HD PDS (Daphne) team
          • ND readout development
      • Work starting on porting timing firmware to MIB (MicroTCA inteface board)
        • MIB needed for PD-II (to replace existing h/ware)
      • Working on specifications for enhancement to protocol
        • Developed in light of PD-I experience
    • 08:00 08:15
      Integration 15m

      Integration status at:
      - CERN
      - Bristol
      - UPenn
      - ICEBERG

      Speakers: Kunal Kothekar, Roland Sipos (CERN), Shyam Bhuller (University of Bristol)
    • 08:15 08:20
      AOB 5m