Upstream DAQ Meeting

Europe/Zurich
Jim Brooke (University of Bristol), Roland Sipos (CERN)

 

1. Timing

  • Software is all in shape in dunedaq-2.8.0 (Stoyan)
    • Need to understand integration with CCM.
  • Had to port firmware to a new FPGA dev-board (for test stands etc), because previous board unavailable
    • Working firmware available, needs to be cleaned up and tagged etc.
  • Working on integration with DAPHNE (Timing sys people in support)
    • Some discussion about self-triggering (Inis asked).
  • Already integrated with optical calib modules at Argonne (not much support was needed)
    • Request a report on status of integration in UD meeting (look in FD HD PDS session).
  • Firmware work ongoing (RAL TD) to support final hardware
    • Once complete, we will be in a position to swap support at coldboxes.
    • Planning required.  To discuss in future UD meeting.
  • Vertical drift ?
    • Tests with WR ongoing. Locked DTS to WR, need to show the other way round.
    • Have a small recap meeting in the coming week.
    • Presentation in future UD meeting.

 

2. Trigger Primitives

  • dtp-firmware 1.2.0 ready for a while now.
    • input/output format changes (GBT to 32bit axis).
  • TP output format
    • Firmware implemented.
    • Software tests suggest new format looks good.
    • Schedule presentation (once finished).
  • WIB2 : dataRx ready, unpacker ongoing
  • Integration with FELIX (felix-pie)
    • Basic structure works.
    • Tried generating a 12 link build (6 links/SLR). 6th link for TPs.  Allowed to test IP bus integration.  (Everything except the actual TPG).
    • See some block errors when sending data to CR.  Highlights a problem with FLX interface that needs to be resolved.
      • Need to decide solution.  Should contact FLX FW people to discuss.
  • Validation
    • Kunal has a document on verification and validation.  Discuss in small group, then implement.

 

3. Readout FW

  • Need to follow up on 4.8 GB/s link merge request to FLX repo
  • Patch we need to get into FLX master, since Phase 2 upgrade links are scrambled (for us).

 

4. Readout SW

  • flxlibs needs proper integration with CCM for card control.  Low level tools still called manually.
    • Discuss with CCM
  • Packages need some re-factoring
    • Front end specialisations should not be in same place as templates
  • SNB recording demonstrated on Cascade Lake
    • 75% of memory bandwidth used
    • Also responding to 50Hz triggers
    • Next year can move to in-depth performance studies, after coldbox support over

 

5. Ethernet readout

  • Simple test application using dpdk driver
    • Used a simple ASIC-based NIC
  • Some thoughts in UK to figure out how to integrate TP FW with Ethernet readout card

 

5. Operations

  • Several test activities that we need to support at CERN over coming months
    • HD coldbox
      • Starting mid Oct
    • VD coldbox (top)
      • Starting mid Nov
    • Vertical slice
      • Schedule ?
    • NP02 PDS
      • 3 SSPs moved from NP04 to NP02
      • Currently read out using artdaq, but need to switch to dunedaq.
      • Schedule ?
  • Need to understand Timing sys configuration
    • CE and readout boxes understood
  • People available to support operations
    • Stoyan Trilov (Timing)
    • Anders, Florian, Roland (Readout/SW)
  • How much support effort can be done remotely ?
    • Not much during the intensive testing phase of coldboxes

 

 

 

There are minutes attached to this event. Show them.
    • 15:00 16:00
      General news and update 1h

      Open discussion on the current status of the timing and readout systems, including testbeds to be supported during the winter.

      Speakers: Jim Brooke (University of Bristol), Roland Sipos (CERN)