Upstream DAQ Tech meeting

Thursday 14 Oct 2021, 07:00 → 08:21 US/Central

 

https://cern.zoom.us/j/68022868314

 

07:00 → 07:15 Current sprint

Consolidation release dunedaq-2.10.0 / FW-2.0.0

Main objectives
- TPG integration
- Ethernet readout (only software for now)

Speakers: Ivana Hristova (STFC RAL), Jim Brooke, Dr Konstantinos Manolopoulos (Rutherford Appleton Laboratory), Konstantinos Manolopoulos (Rutherford Appleton Laboratory), Roland Sipos (CERN), Stoyan Trilov

TP integration

• felix-pie
  • Updated wibulator with axis32b fifo so prog-empty signal is present going back to CR for 6th link readout on debug pod
  • Built and packaged new felix-pie build with updated debug pod and link copy block
  • Currently testing on felix card in 105
  • if tests OK, should be ready to go
• dtp-firmware
  • added the 32baxis_fifo at the end of CRif
  • tests were ok
  • in the process of updating the crif testbench
  • will need to add signals to top level
  • then ready to test 1 link FELIX build

 

Ethernet readout

• tbd what should go into 2.10.0
• will report on plans in a Tuesday meeting in next 1-2 weeks

 

07:15 → 07:30 Timing

Technical developments & future plans

Speakers: David Cussans (University of Bristol), Stoyan Trilov

* Stand-alone IPbus design ported to MIB ( by AB to test Ethernet connection). Will be tested in Bristol by DC

* AB continuing to port fanout design to MIB

* DMN and ST have added ability to generate random triggers to HSI design. Software support still needs to be done & tested.  Q - what is deadline for 2.8.1 ?  follow up with AT.

* Moving on from basic tests of WR-DTS stability to configurations more like the DUNE setup.  GPS-DO --> DTS master --> DTS endpoint --> WR master --> VD top TPC . Initial results encouraging (need to adjust timing/polarity of 1PPS signal from our DTS endpoint to be compatible with WRS

** In addition to testing stability of clock/sync need to define interface between DTS and endpoints using WR to ensure it is possible to write the value of the DTS sample counter into the data.

* Spreadsheet of hardware CB tests is needed where (thanks to RS, JB) is being populated with details of timing hardware.

* Need to purchase some more fibre splitters and fibres. Need to check length needed for VD CB.

07:30 → 07:45 Readout (FW & SW)

Technical developments & future plans on Readout Subsystem.

Speakers: Antony Earle (University of Sussex), Filiberto Bonini (Brookhaven National Laboratory), Mr Florian Grotschla (CERN), Ivana Hristova (STFC RAL), Konstantinos Manolopoulos (Rutherford Appleton Laboratory), Konstantinos Manolopoulos (Rutherford Appleton Laboratory), Roland Sipos (CERN), Shyam Bhuller (University of Bristol)

 

07:45 → 08:00 Trigger Primitives (FW & SW)

Technical developments & future plans on TP specific firmware and software.

Speakers: Antony Earle (University of Sussex), Ivana Hristova (STFC RAL), Konstantinos Manolopoulos (Rutherford Appleton Laboratory), Kunal Kothekar

TP format update

• branch updated by Florian and ready for testing performance using the old/new TP format 
• at the moment running the branch on local machine and making some test scripts
• first aim to measure the relative post-processing (unpacking) overhead when
• using the old TP format compared to the new TP format     
• later also check the relative fraction of resources spent on the unpacking
• stage compared to other post-processing functionlaity, such as stitching, triggeralgs::TriggerPrimitive, TPSet
• finally aim to run more realistic test on dedicated machine which properly  
• accounts for handling the actual raw data streams

 

WIB2 support

• last piece is unpacker.  changes basically done, some issues with regression testing to be resolved.

08:00 → 08:15 Integration

Integration status and upcoming tasks at:
- Neutrino Platform
- CERN DT-DI lab
- Bristol
- UPenn
- ICEBERG

Speakers: Kunal Kothekar, Roland Sipos (CERN), Shyam Bhuller (University of Bristol)

CERN

• moved FLX card for felix-pie integration to new server (where?)
• 10Gbps switch not working (unclear)
• Swapped servers (-30 instead of -26) due to network connection
• Verified can record data from links in VD-CB, HD-CB
• Issues with NP02 SSP readout - found a bug
  • SSP modules not ready yet.
• Will test randoms from HSI
  • Ultimately all setups will need this
  • Do we want to do hardware signal timestamps anyway?  VD-CB?
  • Will need to move FMCs to each setup for HSI.
    • Could take them from WR lab if things go well tomorrow ?
    • Will clarify priorities for HSI among HD-CB/VST/NP02
• Need a machine to drive JTAG to VD-CB TLU

 

DAPHNE integration (@ICEBERG ?)

• Having trouble getting endpoint clk locked to master
• Will try master in loopback

 

08:15 → 08:20 AOB