Upstream DAQ Tech meeting

Thursday 28 Oct 2021, 07:00 → 08:31 US/Central

 

https://cern.zoom.us/j/68022868314

 

07:00 → 07:10 Current sprint

Operations release dunedaq-2.8.1
- HSI random generation

Consolidation release dunedaq-2.10.0 / FW-2.0.0

Main objectives
- TPG integration
- Ethernet readout (only software for now)

Speakers: Jim Brooke, Roland Sipos (CERN)

Current sprint

• 2.8.1
  • HSI random support added
  • Readout seems OK
• 2.10.0
  • Minor updates to CR interface (KM), updating testbench to match
    • Will merge to master, then proceed to integrate TPG with felix-pie
  • Need to push on Ethernet readout demonstrator (dpdk)
  • SNB storage will be an official feature, so needs to be pushed
  • Can we make progress towards RC integration ?

 

Integration

• EHN1
  • Last couple of days : VST readout working (WIBs intended for HD-CB), generated many test configs w DQM etc., VD-CB WIB readout is working. NP02 SSP readout "working", but no feedback from experts.
  • Next days : will test HSI random trigger.
  • SSP HW signal trigger?  Sounds like a stretch...
• Bristol
  • WR switch on order, expected next week.  Not yet able to replicate WR setup, but can run some useful long-term stability tests of DTS/WR.
  • Recorded RAW file with 2.8.0 - some issues, investigating (KK)

 

Round Table

• Timing
  • Progress with MIB FW; discovered some HW issues to workaround.  Will need to make HW changes in respin.
  • No more FMCs, and some components now out of stock/long lead times.  Will engage help of DAQ management.
• Readout FW
  • Nothing to report.
• Readout SW
  • Will need to add packages to support Ethernet readout ? JB/RS to write down a list of what's needed.
• Trigger Primitive FW
  • WIB2 support - broken dep files need to be fixed. KM/KK looking into it.
  • Config - significant progress; EM could write config values and see it being used in simulation. Once happy with pedestal block will proceed with FIR, threshold.
  • Induction wires - conceptual design for separation from collection wires, not yet implemented. Bottom of priority list. Will pick this up once TP/FLX integration done.
• Trigger Primitive SW
  • Performance measurements of TP processing ongoing; useful input after talk last week.
  • Added description of TP readout validation procedure to document.
  • Adding stitching to dtp-simulation; will use to validate the dunedaq readout implementation.
  • Adding to validation document; will finalise it and present in main UD meeting soon.

07:10 → 07:20 Integration

Integration status and upcoming tasks at:
- Neutrino Platform
- CERN DT-DI lab
- Bristol
- UPenn
- ICEBERG

Speakers: Jim Brooke, Roland Sipos (CERN)

07:20 → 07:59 Round table

Looking beyond the current sprint, at planned development, upcoming issues/challenges etc.

07:59 → 08:00 AOB