Upstream DAQ Tech meeting

Europe/Zurich

Current sprint - 2.10.0

  • TP integration
    • 2-link FELIX build lock-up understood. CR expects super-chunk packets, TPG pod expects WIB packets. Workaround - re-generate tlast at the end of every WIB packet for TPG input. Seems to work - no lock ups.  Need to understand longer term solution with FELIX devs.
      • Tony will make a tag & provide bitfiles for testing.
      • Verify this with low-level tools in 2.8.0
    • TP software (Ivana). Branch ready with TP unpacking (old/new formats), generation of TPs in DS formats, stitching algorithm (works without crashing, but validation ongoing). 
  • Consolidation branch ready for 2.10.0 (Florian). inc SNB readout changes, Ivana's changes. Breakout into new packages will come in next week.  flx-card-controller DAQ module in flxlibs.

Stretch goal RC integration.

 

Integration

  • CERN NP : DAQ running nicely.
    • HD-CB electrical connection issue with APA. Taking APA out. No need for support for time being
    • VD-CB have seen tracks. No need for support for time being.
  • Bristol
    • Xilinx U50 on order + programming cable for Ethernet DAQ
    • Mellanox 100GB/s card ordered to act as data source.

 

Timing

  • Established ethernet communications with MIB. Took longer than expected due to support of timing integration by users.
  • MIB firmware work delayed as engineer is out of action following bike accident.
  • Timing users having trouble installing software / get stuck with things like cvmfs. Will add instructions from DAQ.
  • Will need to dismantle WR lab setup at some point to recover FMCs for use in NP setups.
  • Will present plans for uTCA commissioning week after next.

 

Readout FW

  • 4.8Gb/s link MR has been accepted.
  • This means we need to rebase - Tony will do this, query priorities.
    • Prioritise 10 link build, but try a rebase build before Christmas... Discuss next time

 

Readout SW

  • Busy with 2.10, nothing to discuss

 

Trigger Primitive FW

  • WIB2
    • Dependency trouble reported by Kunal with WIB2 tests. KM investigating.
    • Question about 14 bits over 12, need confirmation. Can we get a clear statement, rather than just off the cuff statements in a meeting.
  • Config
    • Integrated ped sub value writing into sim/ZCU102, seems to work
    • Currently working on thresholds/FIR

 

Trigger Primitive SW

  • Nothing beyond 2.10.0 envisaged
  • Validation.
    • Kunal working on addition to dtp-simulation which will read in raw binaries from the dunedaq readout and extract WIB/TP packets, for use in emulator comparison.
    • Beyond that we will want a version that can run in production in dunedaq environment, for in-depth validation and eg. collection of discrepancies. Should be able to re-use the SW TPG, but will need modifications, and also need a module that will do the comparison and take action.
There are minutes attached to this event. Show them.
    • 1
      Current sprint

      dunedaq-2.8.2
      - updates to readout for new data formats
      - timing opmon issues ?

      dunedaq-2.10.0
      - TPG integration
      - Consolidation & refactoring
      - SNB writer update

      Stretch goals :
      - RC integration
      - Ethernet readout

      Speakers: Jim Brooke, Roland Sipos (CERN)
    • 2
      Integration

      Integration status and upcoming tasks at:
      - Neutrino Platform
      - CERN DT-DI lab
      - Bristol
      - UPenn
      - ICEBERG

      Speakers: Jim Brooke, Roland Sipos (CERN)
    • 3
      Round table

      Looking beyond the current sprint, at planned development, upcoming issues/challenges etc.

      • a) Timing

        Hardware
        SW packages : timing, timinglib

        Speakers: David Cussans (University of Bristol), Stoyan Trilov
      • b) Readout FW

        firmware : FELIX core

        Speaker: Filiberto Bonini (Brookhaven National Laboratory)
      • c) Readout SW

        packages : readout, flxlib

        Speakers: Ivana Hristova (STFC RAL), Roland Sipos (CERN), Shyam Bhuller (University of Bristol)
      • d) Trigger Primitive FW

        packages : felix-pie, dtp-firmware

        Speakers: Antony Earle (University of Sussex), Konstantinos Manolopoulos (Rutherford Appleton Laboratory), Kunal Kothekar
      • e) Trigger Primitive SW

        packages : readout (TPG), dtp-control, dtp-simulation

        Speakers: Ivana Hristova (STFC RAL), Jim Brooke, Kunal Kothekar
    • 4
      AOB