Chris
Moved from reference QDMA design to minimal design with user logic. Now integrating the 100G ethernet core. Also switched to 16 Gen4 lanes.
Q - we will want to very/optimise the FW+SW for DMA transfer bandwidth, any thoughts about this ? Will it be simple to use the 100G ethernet core, or would it be useful to include some data generation buffers ? Following discussion - plan is to put same data generation for separate card into U50.
Roy
wants to move towards writing dpdk code to demonstrate transfers, but needs a data source. So he will integrate the data generator from TD into Chris's minimal design, in parallel with Chris integrating the 100G core.
Alessandro
is looking at integrating ipBus over QDMA.
David
planned to use a 100G NIC as data source, with direct attach cable. Rob suggests to use optical, not electrical.
AOB
Jim will contact Tom Williams about a talk on ipBus