DUNE DAQ Hardware/Firmware/Interfaces Meeting (22 Jan 2019)
Babak Abi gave a report on progress on the PBM
updated pinout and mechanical position to match Felix demonstrator
Working on routing
in two weeks - ready to send out for review in 2 weeks. 5th Feb. BA to send E-mail. DGC to forward to RAL in order to arrange design review
Joel Greer gave a status report on hit finder
match of f/ware and s/ware implementation. Matches in most regards.
no need to save state between packets
For more details see slides.
Kostas M. gave a report on pedestal finding and filtering
pedestal subtraction finished.
integrated with filter
some bug finding.
integrated hit finding block. Combined design can be simulated.
Erdem M. gave a report on Buffer management
40 channels. Enough for one APA
Logic at 200MHz, DRAM interface at 300MHz. AXI-Word length 512 bits ( on KCU105 ).
Sending to buffer DRAM in 2kbyte chunks
Keeping FIFO (in FPGA memory) to store length of chunks . Big enough to store data for 10-seconds of data.
Respect channel boundaries
Have time-out which allows less than 2k if data flow to input slow
Reading same amount as written.
EM to check that it is possible to fit a FIFO large enough to store 10 seconds worth of chunks.
Roy Wastie gave a short report on writing to SSD from Zynq ARM core. Looks like it will be necessary to write directly from FPGA fabric to approach theoretical speed.