HEP-IC Workshop 2017

Session

New developments, trends and plans

5 Oct 2017, 08:00

Redwood Rooms Bldg 48 (SLAC National Accelerator Laboratory)

Contribution list Timetable

21. Introduction

Paul O'Connor (BNL)

05/10/2017, 08:30

22. Digital-on-top Mixed Signal Design

Mark Horowitz (Stanford University)

05/10/2017, 08:40

23. Trends in pixel readout chip designs for high rate and radiation

Maurice Garcia-Sciveres (LBNL)

05/10/2017, 09:00

24. Precision Timing in HEP experiments

Prof. Gary Varner (University of Hawaii)

05/10/2017, 09:20

26. Front-end in extreme conditions

Dr Shaorui Li (BNL)

05/10/2017, 09:40

27. Rad-hard methodology and cad tools

Sandeep Miryala

05/10/2017, 10:00

28. Advanced Interconnections between Sensors and Integrated Circuits

Chris Kenney (SLAC)

05/10/2017, 10:40

29. 3D-IC status and trends

Dr Ronald Lipton (Fermilab)

05/10/2017, 11:00

30. Content addressable memories for HEP

Dr Ted Liu (Fermilab)

05/10/2017, 11:20

31. Information-centric analog interfaces

Boris Murmann (Stanford University)

05/10/2017, 11:40

32. Cadence: trends in CAD tools and services

Mladen Nizic (Cadence)

05/10/2017, 13:00

33. MOSIS technology Roadmap

Mr Russ Pina (MOSIS Service)

05/10/2017, 13:20

34. Roundtable

Paul O'Connor (BNL)

05/10/2017, 13:40