Name: VD PD CE Mtg
Start: 2021-03-31T11:00:00-05:00
End: 2021-03-31T13:00:00-05:00
Location: No location set

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Ryan reviewed R&D schedule/plan: https://indico.fnal.gov/event/48193/contributions/210352/attachments/141198/177729/VD_PDS__Baseline_Module_Sketch_and_Timeline.pdf
The voltage and current requirements for our favorite phase 1 candidates should be relayed to Bill Pellico.
April seems to be test/daughter PCB month. We are launching a lot of PCB designs now. CryoCAPTAN is a simple motherboard testbed using Xilinx Artix 7 that has been verified to 30 minutes at FNAL.Andres QP presented update on ADC and FPGA cold tests.
Alan presented update on digital optical transmitter.
Sabrina presented update on analog optical transmitter.
Gustavo presented brief status of work with Dante on passive ganging.
We established a google docs database for collective memory:
- 77K Qualified Components Database: https://docs.google.com/spreadsheets/d/1dCKDbuXOuSvq9h1HQ2d9sXCRqmNE4AAi7NyTwuSiF2Q/edit?usp=sharing

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