Upstream DAQ Tech meeting

Thursday 24 Jun 2021, 07:00 → 08:21 US/Central

 

https://cern.zoom.us/j/68022868314

 

07:00 → 07:15 Current sprint

dunedaq-2.8.0 / FW-2.0.0

Main objectives
- TPG chain

Speakers: Ivana Hristova (STFC RAL), Jim Brooke, Dr Konstantinos Manolopoulos (Rutherford Appleton Laboratory), Konstantinos Manolopoulos (Rutherford Appleton Laboratory), Roland Sipos (CERN), Stoyan Trilov

07:15 → 07:30 Timing

Technical developments & future plans

Speakers: David Cussans (University of Bristol), Stoyan Trilov

Firmware/Software

1. Working on features for 2.8 release
   1. MAC address from PROM ( uses rarpd to set IP )
   2. FIB integration
   3. AFC integration
   4. Infrastrucuture to build both 62.5MHz ( ProtoDUNE-2 , WIB2 ) / 50MHz (WIB1) variants of firmware
2. Debugging return path from timing endpoint --> master (problem believed to be understood)
3. Port of reference firmware to Digilent Nexsys Video board has been "done" (but can't be tested until Adam Barcock at RAL is registered as a CERN user and can have write access to Gitlab repos.)

Integration

Defining set-up for quick test of DTS <--> White Rabbit stability

Aim to perform test next month

Some issues about integrating with VD plans (what hardware will be where, when)

07:30 → 07:45 Readout (FW & SW)

Technical developments & future plans on Readout Subsystem.

Speakers: Antony Earle (University of Sussex), Filiberto Bonini (Brookhaven National Laboratory), Mr Florian Grotschla (CERN), Ivana Hristova (STFC RAL), Konstantinos Manolopoulos (Rutherford Appleton Laboratory), Konstantinos Manolopoulos (Rutherford Appleton Laboratory), Roland Sipos (CERN), Shyam Bhuller (University of Bristol)

Firmware (K. Manolopoulos)

• Intermediate firmware release planned for end of June
  • this release will include the change from 33b gbt to 32b axis format
  • corresponding changes in dpt-simulation and dtp-controls
  • change in the TPs output format (if that has finished and tested by then)
• Currently going through the recipes & testbenches for this release
  • identified changed that need to happen in the hitFormatter.py to validate the output of a full HF chain
• Configuration Block: W.Wulff did some bug fixing and provided us with a user's guide.
  • E. Motuk is now taking over to test and verify the CB's functionality
• WIB2 Data Reception work to integrate in a single block with WIB1 ongoing

Felix-pie (A.Thea, A.Earle)

• Demonstrated basic interface capability using new ipbus stream interface block in VC709 test card, which reads ipbus packets from wupper fifos using fromHost DMA transfer and writes results back using toHost DMA
• Basic implementation lacks ability to control packet flow from host so redesign was planned of the ipbus stream if block
• Further discussion today led to change in plan to allow for faster felix+tp integration. Decided to revert to interface used in protoDUNE 1. Frans has agreed to add ipbus ram registers into phase 2 address table
• Plan now is to integrate the new address table, generate a test build and port the software to allow communication

07:45 → 08:00 Trigger Primitives (FW & SW)

Technical developments & future plans on TP specific firmware and software.

Speakers: Antony Earle (University of Sussex), Ivana Hristova (STFC RAL), Konstantinos Manolopoulos (Rutherford Appleton Laboratory), Kunal Kothekar

TP simulation and release (I. Hristova)

- Generated WIB2 DTB (the old DPR) test patterns for Francesco Gonnella and Mattia Barbanera

- Added an option for convering sink 32b firmware output to hitFormatter (dpt-simulation)

- Following Alessandro's comments we should move dtp-simulation from Python2 to Python3

- In discussion with Kostas decided to have the next dtp-release by end of June

08:00 → 08:15 Integration

Integration status at:
- CERN
- Bristol
- UPenn
- ICEBERG

Speakers: Kunal Kothekar, Roland Sipos (CERN), Shyam Bhuller (University of Bristol)

Bristol Test Stand:

What has been done:

 - ran Instructions from "Instructions for setting up a v2.6.0 development environment". Got nanorc to work, still need to understand exit/error codes

 What needs to be done:

 - try new v1.1.2 version of felix UPS product, check for truncation errors

 - Compare readout from ZCU to the FELIX emulator

 - Get info on how to use nanorc to readout data from FELIX card

- get the wave captures from the debug cores, to test the vanilla bit file.

08:15 → 08:20 AOB