Conveners
Readout and ASIC: Readout and ASIC - 1
- Mitch Newcomer (U.Penn)
Readout and ASIC: Readout and ASIC - 2
- Gabriella Carini (Brookhaven National Laboratory)
Readout and ASIC: Readout and ASIC - 3
- Mitch Newcomer (U.Penn)
Readout and ASIC: Readout and ASIC - Roundtable
- Gabriella Carini (Brookhaven National Laboratory)
Description
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The VMM3a is a System on Chip (SoC) custom Application Specific Integrated Circuit (ASIC). It is the production version which will be used as the front ASIC for both Micromegas and sTGC detectors of the ATLAS Muon New Small Wheels upgrade. Due to its highly configurable parameters it can be used in a variety of tracking detectors and it is already proposed for another experiments. It is...
The ITkPix-V1 readout front-end (FE) chip, based on 65 nm CMOS technology, is designed by the RD53 collaboration as the pre-production chip for the upgraded ATLAS Inner Tracker Pixel detector operating with extreme rates and radiation at the High-Luminosity LHC. The ITkPix-V1 chip uses a novel differential analog FE design featuring low noise and small time-walk. ITkPix-V1 was submitted in...
The luminosity of the High Luminosity Large Hadron Collider (HL-LHC) will be increased to 7.5×10$^{34}$cm$^{−2}$s$^{−1}$ in Run 4 that will start in 2027. The expected integrated luminosity will be 3000-4000 fb$^{-1}$ at the end of the HL-LHC operation. The liquid argon calorimeter consists of electromagnetic barrel, electromagnetic end-cap, hadronic endcap and forward calorimeter. The...
In HEP experiments, detector data communication is one of the key R&D areas. This is especially important when the operating environments inside the detectors preclude the use of COTS in these link systems. ASICs and optical modules are being developed to meet the challenges of detector upgrades in the LHC. This effort has been led by the CERN common projects GBT/lpGBT and Versatile Link/VL+. ...
Future long baseline neutrino experiments such as the Deep Underground Neutrino Experiment (DUNE) pose challenges for development of readout techniques for multi-kiloton LAr Time Projection Chambers (TPC). In contrast to wire/strip anode readout, a pixelated readout eliminates disadvantages such as disambiguation in 2D track reconstruction. The Q-Pix Consortium, established in 2019, is...
We present the development of a cryogenic Low-Noise Amplifier (LNA) for the readout of Superconducting Nanowire Single Photon Detectors (SNSPDs). The integrated circuit operates at 4 K and is based on fourth-generation heterojunction bipolar transistors from a state-of-the-art, commercially available SiGe BiCMOS platform, which allows large scale integration and economy of scale. Target...
The MIDNA application specific integrated circuit (ASIC) is a prototype cryogenic skipper-CCD readout chip fabricated in a 65 nm LP CMOS process and intended for the OSCURA dark matter detection project. The MIDNA ASIC integrates four front-end channels designed to interface with the 4000 skipper-CCDs for a 28 gigapixel camera for dark matter detection. Each channel is only 0.156...
At the previous CPAD workshop (Madison, 2019), we presented observation of Pulse-Shape Discrimination (PSD) in segmented plastic scintillator developed at LLNL instrumented with modern photosensors — silicon-photomultiplier arrays.
This talk discusses the progress of various experimental efforts we have pursued for several potential applications of such detectors, ranging from nuclear...
The Baryon Mapping Experiment (BMX) at Brookhaven Laboratory is a 4-dish radio interferometer operating in the frequency band from 1100 to 1650MHz. It is designed as a technical pathfinder for a future cosmic survey using the intensity mapping technique to measure large-scale 3D cosmic structure traced by the redshifted emission of neutral hydrogen (rest frame wavelength 21cm). The array...
During the development of new detectors for future experiments or the Upgraded Collider detectors, the ASIC and sensor development often follow parallel paths. This implies that, for the last stages of ASIC development there often exists a significant body of data obtained with high quality waveform sampling that capture the subtleties of real response of the sensors to various particle...
Recent advances in semiconductor 3D integration technology could enable modularity in sensors: An advanced digital chip may be combined with a separately fabricated analog detector front end and a separate detector. This technology will enable common use of highly capable but expensive digital components across sensing mode (imaging, photon counting, photon timing, etc) and wave band (gamma...
In a multi-channel detector readout system, waveform sampling, digitization and transmitting bits to the data acquisition system constitutes a conventional processing chain. Quantities, such as time-of-arrival and signal magnitude, i.e deposited energy, are estimated by fitting analytical models over the acquired digital data, hence enabling the extraction of signal starting time, peak...
Despite advances in the programmable logic capabilities of modern trigger systems, a significant bottleneck remains in the amount of data to be transported from the detector to off-detector logic where trigger decisions are made. We demonstrate that a neural network autoencoder model can be implemented in a radiation tolerant ASIC to perform lossy data compression alleviating the data...
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