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Upstream DAQ Tech meeting

US/Central
    • 07:00 07:15
      Current sprint 15m

      dunedaq-2.8.0 / FW-2.0.0

      Main objectives
      - TPG chain
      - Ethernet readout (only software for now)

      Speakers: Ivana Hristova (STFC RAL), Jim Brooke, Dr Konstantinos Manolopoulos (Rutherford Appleton Laboratory), Konstantinos Manolopoulos (Rutherford Appleton Laboratory), Roland Sipos (CERN), Stoyan Trilov
    • 07:15 07:30
      Readout (FW & SW) 15m

      Technical developments & future plans on Readout Subsystem.

      Speakers: Antony Earle (University of Sussex), Filiberto Bonini (Brookhaven National Laboratory), Mr Florian Grotschla (CERN), Ivana Hristova (STFC RAL), Konstantinos Manolopoulos (Rutherford Appleton Laboratory), Konstantinos Manolopoulos (Rutherford Appleton Laboratory), Roland Sipos (CERN), Shyam Bhuller (University of Bristol)

      felix-pie

      • Wibulator bug found to be sourcing wrong dtpc_ctrl.vhd file, Fixed and single link debug pod shown to work sucessfully
      • Tested debug pod with 5 links and wibulator on 6th link generating data back to CR and functions correctly
      • Testing build with CR tready signals routed to the processing pod. Block errors are now on the 6th link, (wibulator). Investigating
      • Made an attempt at a single link build with the real tpg processing pod. Built successfully and ipbus communication to sections of the chain work correctly, but when playing emulator data into the link, the chain seems to lock up due to back pressure. Investigating
    • 07:30 07:45
      Trigger Primitives (FW & SW) 15m

      Technical developments & future plans on TP specific firmware and software.

      Speakers: Antony Earle (University of Sussex), Ivana Hristova (STFC RAL), Konstantinos Manolopoulos (Rutherford Appleton Laboratory), Kunal Kothekar

      TP simulation (I.Hristova)

      - new tag for fw release v1.2.0 including

        - updated documentation

        - including CRC and EMUconfig pattern files

        - clean stale branches

       

      TP readout software (I. Hristova)

      - implemented overlay based on FakeCardReader and TPEmulatorModel

      - adding stitiching algorithm as a processing task ongoing

       

      Verification and Validation ( K. Kothekar)

      First draft of the verification and validation document is ready will circulate it for comments.

       

       

    • 07:45 08:00
      Timing 15m

      Technical developments & future plans

      Speakers: David Cussans (University of Bristol), Stoyan Trilov
    • 08:00 08:15
      Integration 15m

      Integration status at:
      - CERN
      - Bristol
      - UPenn
      - ICEBERG

      Speakers: Kunal Kothekar, Roland Sipos (CERN), Shyam Bhuller (University of Bristol)
    • 08:15 08:20
      AOB 5m