DUNE PRR: LArASIC Production Readiness Review

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Cheng-Ju Lin (Lawrence Berkeley National Laboratory), David Christian (Fermilab), Marco Verzocchi (Fermilab), Philippe Farthouat (CERN)
Description

Review of the DUNE-FD TPC Electronics LAr frontend ASIC production readiness


Review Information
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Final Committee Report

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Monday March 7, 2022

 

 

8:30 AM → 9:00 AM

Overview, LArASIC requirements, and recommendations from FDR30m

Speaker: Cheng-Ju Lin (Lawrence Berkeley National Laboratory)

PRR_LArASIC_Intro_03-07-2022.pdf

Question: What is the status of packaging?

Answer: We are still waiting for the lead frame from IEC[?] after that we can proceed with the packaging companies.

 

Srini: What is the overall strategy – you plan to place your production through Moses vs EuroPractice and Moses has not sent you any indication of not taking orders in the future – so is the strategy to be ready for procurement put to hold off on the order?

Answer: Senior management doesn’t want to take the risk, we will not hold of on procurement, we would like to proceed with procurement early if this committee decides we are ready.

 

Jim Mateyack: In the recommendations from the FDR – a QC plan will include test equipment validation – do we know when the estimate of having the testing equipment ready?

Answer: Shanshan will address QC – right now for the QC of the current batch engineering chips we are using the same technique as with the ProtoDUNEs [manual?] - we are developing a robotic system to do the full QC but it is not ready – still in design phase. 

 

 

9:00 AM → 9:45 AM

LArASIC performance and FEMB integration tests45m

Speaker: Shanshan Gao (Brookhaven National Lab)

LArASIC_PRR_Review_03072022_r1.pdf

 

Jim: Slide 16 – you mention ESD damage during handling – did we change the handling process at all as well as make the design more ESD robust? Was this a process problem?

Answer: We handle the P5 and P5b the same way and follow ESD protection best practices. Especially in winter more susceptible to the discharge.

 

Alessandro: Slide 13 – when you say P5 LArASIC at 3V at 300 hrs? Why 3V why 300 hrs? What is the goal of the test?

Answer: I tested many chips and I found the maximum is 3V that the LArASIC can sustain for the accelerated aging tests. Slide 12 the lifetime is inversely proportional to the appllied voltage so to do the accelerated studies we chose the maximum voltage the chip can operate at for aging studies

 

Alessandro: Slide 13 you mention that the operating voltage is 1.8V for the CMOS chips? The recommendaiton is don’t go beyond 10%. You only tested  3 chips.

Answer: The question is how high a voltage we can go to accelerate the aging tests – so we pushed it to 3V instead of the recommended 10% over design voltage.

 

Mitch: I was interested in interference noise from the other FEMB components – did you show results or measurements on that? Is there FE noise associated with register switching during configuration?

Answer:  We did not observe any FE noise from interference during configuration – we use the same configuration during testing as for the detector operations.

 

Tim: Encouraging on slide 23 to see testing with full FEMB. This is an FEMB with the latest chip on it P5b – this cant be the latest COLADC?

Answer: All 3 ASICs on the FEMB are the final versions of all 3 ASICS: LArASIC, COLADC and COLDATA.  What you see on slide 23 is the design that will be used in ProtoDUNE II and if it passed the tests in PRotoDUNE that will be the design used in the final Far Detector.

 

Tim: Do you plan on testing LArASIC alone or LArASIC and COLDATA at the same time?

Answer: We plan to do separate tests on individual chips but we plan to use exactly the same test board for all 3 chips – but for example when we test LArASIC we use a golden COLADC and COLDATA, if it is testing a COLADC then we use the same LArASIC golden chip ...etc. We have enough COLADC and COLDATA to support the testing of all LArASIC up front but the testing schedule has not been finalized [or the robotic system].

 

Tim: Slide 21 – can you say something about why channel  0 and 8 are showing more cross-talk than other channels?

Answer: We know that channel 0 and 8 have higher non-linearity and the neighbouring channels are the ones with the higher cross-talk. The cross-talk specification is < 1% with a target of 0.1%. Despite the higher cross-talk on the neighbouring channels it is still < 1% and meets spec. We know the cross-talk is dominated by the ADC.

 

Terri: Page 16 ESD damage – ask if there is a written document that shows how the chips are handled – there is more that you can do than just wear a wrist strap – it is concerning that we are getting this much ESD damage. ESD is death by  a thousand cuts so you may not see some damage that crops up later.

 

Answer: We have a document on the procedures that we will supply. We also point out that the P5b chip that we plan on doing does not show the ESD damage. The P5b are more testing in the engineering run compared to P5 and none of them have shown any damage – so we are seeing encouraging results that the enhanced P5b ESD protection.

 

Srini: It bothers me that the handling procedure has not been improved rather than relying on better ESD protection on the chip alone.

Answer: We are following all best practices for ESD handling so we don’t know if there is more that we can do.

 

Philippe: During the FDR there was a concern on the calibration capacitor that varies chip to chip – have you done more to fix this?

Answer: For the QC test we will test the capacitor for all chips. We traced the variation observed prior to the FDR to the contact with the chip with the testing socket. The variation of the capacitors on the chips is actually small.

 

Alessandro: What is the change in the ESD protection between P5 and P5b – what is enhanced – did you degrade the ESD protection from the manufacter recommended for P5? Did you take the ESD standard from the manufacture?

Answer: The ESD protection circuit was developed by our LArASIC designers – an in house design. Mostly titon gate – just the size of the transistor. We cannot use the standard protection scheme because any resistance in series with input will reduce the low-noise performance of the chip – anything in excess of 10 ohm. Any ESD protection can also leak and reduce the chip performance. So we use transistors and played with the size of the transistors and we came up with 30X size increase compared with what we had in the beginning.

 

Srini: Do you have the comparison of P5 and P5b noise?

Answer: Basically you cant see any difference in the noise between the two versions.

 

Srini: What is the final tests to qualify the chip for DUNE?

Answer: ProtoDUNE II is the final test. We cant launch production fast so we are sticking with the same mask with both P5a and P5b – also cost benefit analysis indicates it is not worth going with a new mask given the number of chips needed for both FDs.

 

 

10:00 AM → 10:20 AM

LArASIC procurement plan20m

Speaker: Hucheng Chen (Brookhaven National Lab)

FEASICPRR.20220307.v2.pdf

 

[Some discussion of plans for FD3 and FD4. FD3 would most likely be a vertical drift design like FD2 so if nothing changes there is enough for the bottom electronics which use the same readout board and chips as FD1. The top electronics use a different FE readout. FD4 is not on the horizon]

 

Mitch: Are the process parameters provided for each wafer from STSMC?

Answer: Yes

 

Philippe: You need to assume loss from dicing

Answer: We expect yield 90-95% per wafer

 

Tim: The FD3, 4 plan [use the extra P5a chips on the wafer] is the plan to dice them and package them as well?

Answer: We have enough storage for all the wafers that is not a problem. A different round of packaging would have to be developed for FD3 and 4.

 

Philippe: The simplest would be to package everything including P5a.

Answer: The current focus is getting it done for FD1 and FD2. The plans for FD3 and 4 are too uncertain.

 

 

10:50 AM → 11:20 AM

LArASIC QC Plan30m

Speaker: Shanshan Gao (Brookhaven National Lab)

LArASIC_QC_plan_03072022_r1.pdf

 

Mitch: You will not be testing the leakage on the LArASIC chip?

Answer: We did earlier tests when we suspected ESD damage, but we will not be doing it for the production chips.

 

Philippe: Earlier in the development you put test transistors to test the performance in the cold – is this implemented?

Answer: We didn’t add this compensation circuit to P5b and there is no need to place them on the final production.

 

Philippe: So you do not see a need to monitor the performance in the cold to understand the technology?

Answer: The LArASIC has not varied from one run to the other, once we understood the variability of the compensation circuit we didn’t see the need to add the compensation circuit. The experience from the analog perfomance in the cold from the very early version till now we did not see any difference in noise perfomance. All circuitry was extensively modeled using foundry models at cryo temperatures for 180nm. The data point of models was not available before early 2021 but now we have it.

 

Philippe: When do you think you will be ready with test equipment?

Answer: The schematic is there modulo some final tuning. The robotic hardware is there but the focus now is on the testing box. By late summer we expect to go into production of the robotic testing system. If everything goes smoothly we expect by early fall to be shipping the testing setup to the various sites. So in time for the production run.

 

PaulL: The FEMB boards assembled so far – hand assembled?

Answer: 1 of 7 assembled by our techs from an earlier board the rest – the 6 shown are all assembled by machine at an assembly house.

 

Paul: Some chips need to be used up for qualifying the assembly – there are no numbers for that – is it insignificant or from the engineering run?

Answer: It is a small number and not explicitly included in the accounting – in the noise

 

Tim: WRT to the prep of the robotic system – that timeline is end of the year and that is inline with the DB to store the test results? Is the DB going to be maintained by DUNE for the lifetime of the expt? You will not have a separate DB instance at each site?

Answer: The DB right now is being setup for the current run at LSU – current QC data is stored on site but by the fall we expect the hardware DB will be ready then and already tested with the existing data locally stored. The hardware DB will be centralized and each test site will be uploaded to the centralized DB.

 

Tim: What is the procedure/threshold of not doing the cold test at this stage of the testing? Is it after you test a 1000 chips...?

Answer: We havent yet defined what the threshold is – it is ongoing subject of discussion.

 

Paul: Given the current packaging vendor is not putting serial numbers on the chips – do you have a plan for addressing this?

 

Answer: We do not plan to use GTK the current packager for the final run. Only for engineering – the 2nd half of the engineering run we are going to the final packaging house. For the GTK packaged chips from the early engineering run will will write it by hand on the chip.

 

 

 

11:35 AM → 12:10 PM

Summary and Discussion35m

Speaker: Cheng-Ju Lin (Lawrence Berkeley National Laboratory)

PRR_LArASIC_Summary_03-07-2022.pdf

 

Paul: Queston about P5 (not P5b) - when you send the wafers to get packaged what happens to the other chips – do they stay on the blue tape?

Answer: Long term storage is not a concern – it will become a consortium packaging decision by the time we send the wafer for dicing and packaging?

 

Jim: QC plan verision 2 when will it be available?

Mary: Does the QC including the procedures for robotic testing or only manual testing currently being done?

Answer: There is a version 2 already provided with the official documentation. V2 is to address the issues needed to address the early wafer production. We appreciate any feedback on whether that is sufficient. In terms of the QC steps and issues is the same as version 1. Right now the plan is very high level – we don’t have step by step instructions. DIscussion of the robotic testing is already there.

 

 

 

12:10 PM → 12:30 PM

Executive Session20m

Speaker: Philippe Farthouat (CERN)

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